Metastability refers to signals that do not assume stable 0 or 1 states for a certain duration during normal operation of a digital design.

In multi-clock designs, metastability cannot be completely avoided, but its detrimental effects can be minimized or neutralized through proper synchronization techniques.

📘 Definition from Dally and Poulton

“When sampling a changing data signal with a clock ... the order of the events determines the outcome.
The smaller the time difference between the events, the longer it takes to determine which came first.
When two events occur very close together, the decision process can take longer than the time allotted,
and a synchronization failure occurs.”

⚠️ Synchronization Failure

• Cause: Occurs when a signal from one clock domain is sampled too close to the rising edge of a clock signal from another domain.
• Effect: The output goes metastable, failing to converge to a valid logic state (0 or 1) before the next sampling event.